<dec f='src/src/sys/external/bsd/drm2/dist/drm/nouveau/core/engine/disp/nv50.h' l='32' type='u32'/>
<offset>1536</offset>
<use f='src/src/sys/external/bsd/drm2/dist/drm/nouveau/core/engine/disp/nouveau_engine_disp_nv50.c' l='1568' u='r' c='nv50_disp_intr_supervisor'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/nouveau/core/engine/disp/nouveau_engine_disp_nv50.c' l='1570' u='r' c='nv50_disp_intr_supervisor'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/nouveau/core/engine/disp/nouveau_engine_disp_nv50.c' l='1580' u='r' c='nv50_disp_intr_supervisor'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/nouveau/core/engine/disp/nouveau_engine_disp_nv50.c' l='1597' u='r' c='nv50_disp_intr_supervisor'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/nouveau/core/engine/disp/nouveau_engine_disp_nv50.c' l='1634' u='w' c='nv50_disp_intr'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/nouveau/core/engine/disp/nouveau_engine_disp_nv50.c' l='1636' u='r' c='nv50_disp_intr'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/nouveau/core/engine/disp/nouveau_engine_disp_nvd0.c' l='1190' u='r' c='nvd0_disp_intr_supervisor'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/nouveau/core/engine/disp/nouveau_engine_disp_nvd0.c' l='1196' u='r' c='nvd0_disp_intr_supervisor'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/nouveau/core/engine/disp/nouveau_engine_disp_nvd0.c' l='1205' u='r' c='nvd0_disp_intr_supervisor'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/nouveau/core/engine/disp/nouveau_engine_disp_nvd0.c' l='1225' u='r' c='nvd0_disp_intr_supervisor'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/nouveau/core/engine/disp/nouveau_engine_disp_nvd0.c' l='1310' u='w' c='nvd0_disp_intr'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/nouveau/core/engine/disp/nouveau_engine_disp_nvd0.c' l='1312' u='r' c='nvd0_disp_intr'/>
